HD6417751 Datasheet, PDF (843/1105 Pages) Renesas Technology Corp – SuperH RISC engine

22.1.2 Block Diagram
Figure 22.1 is a block diagram of the PCIC.
Interrupts
PCIC module
Interrupt
control
Internal peripheral
module bus
(Peripheral bus)
Internal
peripheral
module bus
interface
Local
register
Bus request
Acknowledge
PCI bus
PCI bus interface
Local
register
PCI
configuration
register
Data transfer
control
Local
register
FIFO
32B × 2 sides × 6
PCIC bus controller
Local
register
Local bus
Local bus clock
(Bφ) cycle: Bcyc ^Feedback
input clock
from CKIO
Figure 22.1 PCIC Block Diagram
PCI clock
33/66 MHz
(PCICLK)
Rev. 3.0, 04/02, page 803 of 1064