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HD6417751 Datasheet, PDF (1027/1105 Pages) Renesas Technology Corp – SuperH RISC engine
CKIO
Bank
TRr1
TRr2
TRr3
TRr4
TRrw
TRr5
Trc
Trc
Trc
tAD
tAD
Precharge-sel
Address
RD/
tCSD
tCSD
tCSD
tRWD
tRASD
tRASD
tRASD
tCASD2 tCASD2 tCASD2
tRWD
tCASD2
tCSD
tRASD
DQMn
D31–D0
(write)
tDQMD
tWDD
tWDD
tBSD
tDQMD
CKE
DACKn
tDACD
tDACD
Notes: IO: DACK device
SA: Single address DMA transfer
DA: Dual address DMA transfer
DACK set to active-high
Figure 23.32 Synchronous DRAM Bus Cycle: Auto-Refresh (TRAS = 1, TRC [2:0] = 001)
Rev. 3.0, 04/02, page 987 of 1064