HD6417751 Datasheet, PDF (616/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Bit 4—Parity Mode (O/): Selects either even or odd parity for use in parity addition and
checking. The O/ bit setting is only valid when the PE bit is set to 1, enabling parity bit addition
and checking, in asynchronous mode. The O/ bit setting is invalid in synchronous mode, and
when parity addition and checking is disabled in asynchronous mode.
Bit 4: O/
Description
0
Even parity*¹
(Initial value)
1
Odd parity*²
Notes: *1 When even parity is set, parity bit addition is performed in transmission so that the total
number of 1-bits in the transmit character plus the parity bit is even. In reception, a
check is performed to see if the total number of 1-bits in the receive character plus the
parity bit is even.
*2 When odd parity is set, parity bit addition is performed in transmission so that the total
number of 1-bits in the transmit character plus the parity bit is odd. In reception, a check
is performed to see if the total number of 1-bits in the receive character plus the parity
bit is odd.
Bit 3—Stop Bit Length (STOP): Selects 1 or 2 bits as the stop bit length in asynchronous mode.
The STOP bit setting is only valid in asynchronous mode. If synchronous mode is set, the STOP
bit setting is invalid since stop bits are not added.
Bit 3: STOP
Description
0
1 stop bit*¹
(Initial value)
1
2 stop bits*²
Notes: *1 In transmission, a single 1-bit (stop bit) is added to the end of a transmit character
before it is sent.
*2 In transmission, two 1-bits (stop bits) are added to the end of a transmit character
before it is sent.
In reception, only the first stop bit is checked, regardless of the STOP bit setting. If the second
stop bit is 1, it is treated as a stop bit; if it is 0, it is treated as the start bit of the next transmit
character.
Rev. 3.0, 04/02, page 576 of 1064