HD6417751 Datasheet, PDF (1058/1105 Pages) Renesas Technology Corp – SuperH RISC engine

HD6417751VF133
*2
Module Item
Symbol Min Max
DMAC '5(4Q setup
t_DRQS
3.5 —
time
INTC
'5(4Q hold time t_DRQH
DRAKn delay time t_DRAKD
NMI pulse width t_NMIH
(high)
1.5 —
—8
5
—
HD6417751BP167
HD6417751BP167I
HD6417751F167
HD6417751F167I
*3
Min Max
Unit
3.5 —
ns
1.5 —
ns
—8
ns
5
—
t_cyc
Figure
23.64
23.64
23.64
23.69
30 —
30 —
ns
23.69
NMI pulse width t_NMIL
5
—
(low)
5
—
t_cyc
23.69
30 —
30 —
ns
23.69
H-UDI Input clock cycle t_TCKcyc
50
—
50 —
ns
23.65,
23.67
Input clock pulse t_TCKH
width (high)
15 —
15 —
ns
23.65
Input clock pulse t_TCKL
width (low)
15 —
15 —
ns
23.65
Input clock rise
t_TCKr
time
— 10
—
10
ns
23.65
Input clock fall time t_TCKf
— 10
$6(%5. setup
t_ASEBRKS
10
—
time
—
10
10 —
ns
23.65
t_cyc
23.66
$6(%5. hold time t_ASEBRKH 10
—
TDI/TMS setup
t_TDIS
time
15 —
10 —
15 —
t_cyc
23.66
ns
23.67
TDI/TMS hold time t_TDIH
15 —
TDO delay time t_TDO
0
12
ASE-PINBRK pulse t_PINBRK
2
—
width
15 —
0
10
2
—
ns
ns
Pcyc*¹
23.67
23.67
23.68
Notes: *1 Pcyc: P clock cycles
*2 V_DDQ = 3.0 to 3.6 V, V_DD = 1.5 V typ, Ta = –20 to 75°C, C_L = 30 pF, PLL2 on
*3 V_DDQ = 3.0 to 3.6 V, V_DD = 1.8 V typ, Ta = –20 to 75°C, C_L = 30 pF, PLL2 on
(HD6417751BP167, HD6417751F167)
V_DDQ = 3.0 to 3.6 V, V_DD = 1.8 V typ, Ta = –40 to 85°C, C_L = 30 pF, PLL2 on
(HD6417751BP167I, HD6417751F167I)
Notes
Normal
or sleep
mode
Standby
mode
Normal
or sleep
mode
Standby
mode
Rev. 3.0, 04/02, page 1018 of 1064