HD6417751 Datasheet, PDF (213/1105 Pages) Renesas Technology Corp – SuperH RISC engine

7.3 Instruction Set
Table 7.2 shows the notation used in the following SH instruction list.
Table 7.2 Notation Used in Instruction List
Item
Format
Description
Instruction
mnemonic
OP.Sz SRC, DEST
OP:
Sz:
SRC:
DEST:
Operation code
Size
Source
Source and/or destination operand
Summary of
operation
→, ←: Transfer direction
(xx): Memory operand
M/Q/T: SR flag bits
&:
Logical AND of individual bits
|:
Logical OR of individual bits
∧:
Logical exclusive-OR of individual bits
~:
Logical NOT of individual bits
<<n, >>n: n-bit shift
Instruction code MSB ↔ LSB
mmmm:
nnnn:
0000:
0001:
:
1111:
mmm:
nnn:
000:
001:
:
111:
mm:
nn:
00:
01:
10:
11:
iiii:
dddd:
Register number (Rm, FRm)
Register number (Rn, FRn)
R0, FR0
R1, FR1
R15, FR15
Register number (DRm, XDm, Rm_BANK)
Register number (DRm, XDm, Rn_BANK)
DR0, XD0, R0_BANK
DR2, XD2, R1_BANK
DR14, XD14, R7_BANK
Register number (FVm)
Register number (FVn)
FV0
FV4
FV8
FV12
Immediate data
Displacement
Privileged mode
“Privileged” means the instruction can only be executed
in privileged mode.
T bit
Value of T bit after —: No change
instruction execution
Note: Scaling (×1, ×2, ×4, or ×8) is executed according to the size of the instruction operand(s).
Rev. 3.0, 04/02, page 173 of 1064