HD6417751 Datasheet, PDF (421/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Wait State Control: As the clock frequency increases, it becomes impossible to complete all
states in one cycle as in basic access. Therefore, provision is made for state extension by using the
setting bits in WCR2 and MCR. The timing with state extension using these settings is shown in
figure 13.15. Additional Tpc cycles (cycles used to secure the 5$6 precharge time) can be
inserted by means of the TPC bit in MCR, giving from 1 to 7 cycles. The number of cycles from
5$6 assertion to &$6 assertion can be set to between 2 and 5 by inserting Trw cycles by means of
the RCD bit in MCR. Also, the number of cycles from &$6 assertion to the end of the access can
be varied between 1 and 16 according to the setting of A3W2 to A3W0 in WCR2.
CKIO
Address
Tr1
Tr2
Trw
Tc1
Tcw
Tc2
Tpc
Tpc
Row
Column
RD/
D31–D0
(read)
D31–D0
(write)
DACKn
(SA: IO ← memory)
DACKn
(SA: IO → memory)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.15 DRAM Wait State Timing
Rev. 3.0, 04/02, page 381 of 1064