HD6417751 Datasheet, PDF (919/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Bits 31 to 0—PIO Configuration Data (PPDA31 to 0): Read/write register for configuration
data in PIO transfers.
The configuration cycle on the PCI bus can be generated by reading/writing to this register.
22.3 Description of Operation
22.3.1 Operating Modes
The external mode pins (MD9 and MD10) select whether the PCIC operates as the host on the PCI
bus and also select the bus clock for the PCI bus. The mode selection signals input via the external
mode pins are fetched on negation of a power-on reset.
Table 22.8 Operating Modes
MD9
MD10
Operating Modes
0
0
The PCIC host functions are enabled and the external
input via the PCICLK pin is the operating clock for the
PCI bus
1
The PCIC host functions are enabled and the SH7751
Series bus clock (feedback input clock from CKIO pin)
is the operating clock for the PCI bus
1
0
The PCIC host functions are disabled (non-host) and
the input clock from the PCICLK pin is selected as the
clock for the PCI bus
1
PCIC-disabled mode. In this mode, PCIC operation is
disabled
Note: In PCIC-disabled mode, do not attempt to access the PCIC local registers.
In this section, the clock resulting from the above mode switching is known as the PCI bus clock.
Rev. 3.0, 04/02, page 879 of 1064