HD6417751 Datasheet, PDF (292/1105 Pages) Renesas Technology Corp – SuperH RISC engine

3. Internal processor operation stops temporarily, PLL circuit 1 oscillates, and the WDT starts
counting up. The internal clock stops and an unstable clock is output to the CKIO pin.
4. After the WDT count overflows, PLL circuit 2 starts oscillating. The WDT resumes its up-
count from the value set in step 1 above. During this time, also, the internal clock is stopped
and an unstable clock is output to the CKIO pin.
5. After the WDT count overflows, clock supply begins within the chip and the processor
resumes operation. The WDT stops after overflowing.
10.5.3 Changing Bus Clock Division Ratio (When PLL Circuit 2 is On)
If PLL circuit 2 is on when the bus clock frequency division ratio is changed, a PLL circuit 2
oscillation stabilization time is required.
1. Make WDT settings as in 10.5.1.
2. Set the BFC2–BFC0 bits to the desired value.
3. Internal processor operation stops temporarily, and the WDT starts counting up. The internal
clock stops and an unstable clock is output to the CKIO pin.
4. After the WDT count overflows, clock supply begins within the chip and the processor
resumes operation. The WDT stops after overflowing.
10.5.4 Changing Bus Clock Division Ratio (When PLL Circuit 2 is Off)
If PLL circuit 2 is off when the bus clock frequency division ratio is changed, a WDT count is not
performed.
1. Set the BFC2–BFC0 bits to the desired value.
2. The set clock is switched to immediately.
10.5.5 Changing CPU or Peripheral Module Clock Division Ratio
When the CPU or peripheral module clock frequency division ratio is changed, a WDT count is
not performed.
1. Set the IFC2–IFC0 or PFC2–PFC0 bits to the desired value.
2. The set clock is switched to immediately.
Rev. 3.0, 04/02, page 252 of 1064