HD6417751 Datasheet, PDF (788/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Program
execution state
Interrupt
No
generated?
Yes
(BL bit
in SR = 0) or No
(sleep or standby
mode)?
Yes
No
NMI?
Yes
NMIB in
No
ICR = 1 and
NMI?
Yes
Level 15
No
interrupt?
Yes
Level 14
No
Yes
I3–I0* =
level 14 or
lower?
interrupt?
Yes
Level 1
No
Set interrupt source
in INTEVT
No _Yes
I3–I0 =
level 13 or
lower?
interrupt?
Yes
Save SR to SSR;
save PC to SPC
No _Yes
I3–I0 =
level 0?
No
Set BL, MD, RB bits
in SR to 1
Branch to exception
handler
Note: * I3–I0: Interrupt mask bits in status register (SR)
Figure 19.3 Interrupt Operation Flowchart
Rev. 3.0, 04/02, page 748 of 1064