HD6417751 Datasheet, PDF (876/1105 Pages) Renesas Technology Corp – SuperH RISC engine

22.2.15 PCI Configuration Register 17 (PCICONF17)
Bit:
Initial value:
PCI-R/W:
PP Bus-R/W:
31
DATA7
0
R
R
30
DATA6
0
R
R
29
DATA5
0
R
R
28
DATA4
0
R
R
27
DATA3
0
R
R
26
DATA2
0
R
R
25
DATA1
0
R
R
24
DATA0
0
R
R
Bit: 23
22
21
20
19
18
17
16
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
PCI-R/W: R
R
R
R
R
R
R
R
PP Bus-R/W: R
R
R
R
R
R
R
R
Bit:
Initial value:
PCI-R/W:
PP Bus-R/W:
15
14
13
12
11
10
9
8
PMEST DTATSCL1 DTATSCL0 DATASEL3 DATASEL2 DATASEL1 DATASEL0 PMEEN
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 7
6
5
4
3
2
1
0
—
—
—
—
—
—
PWRST1 PWRST0
Initial value: 0
0
0
0
0
0
0
0
PCI-R/W: R
R
R
R
R
R
R/W
R/W
PP Bus-R/W: R
R
R
R
R
R
R/W
R/W
The PCI configuration register 17 (PCICONF17) is a 32-bit read/partial-write register that
accommodates the power management control/status (PMCSR), bridge-compatible PMCSR
extended (PMCSR_BSE), and data power management registers stipulated in the PCI power
management specifications. PCICONF17 is valid only when the PCIC is operating not as the host.
Bits 31 to 24 (data) and bits 23 to 16 (PMCSR_BSE) are not supported. The power management
status is read from bits 15 to 0 (PMCSR).
Bits 1 and 0 can be written to from both the PP bus and the PCI bus. Other bits are fixed in
hardware.
PCICONF17 is initialized to H'00000000 at a power-on reset and software reset.
Rev. 3.0, 04/02, page 836 of 1064