HD6417751 Datasheet, PDF (901/1105 Pages) Renesas Technology Corp – SuperH RISC engine

The DMA transfer counter register [3:0] (PCIDTC [3:0]) specifies the number of bytes for DMA
transfers. This 32-bit read/write register can be accessed from both the PP bus and PCI bus. When
read during a DMA transfer, it returns the remaining number of bytes in the DMA transfer.
The PCIDTC register is initialized to H'00000000 at a power-on reset and a software reset.
Bits 25 to 0 are used to specify the number of transfer bytes. When set to H'00000000, the
maximum 64MB transfer is performed. Since the transfer data size corresponds only to longword
data, the 2 least significant bits are ignored.
Always write to this register prior to starting a DMA transfer. Please re-set this register when
starting a new DMA transfer after a DMA transfer completes.
Bits 31 to 26—Reserved: These bits always return 0 when read. Always write 0 to these bits.
Bits 25 to 0—PIC25 to 0: Specify the number of bytes in DMA transfer. The maximum number
of transfer bits are 64 MB (when set to H'00000000).
Rev. 3.0, 04/02, page 861 of 1064