HD6417751 Datasheet, PDF (118/1105 Pages) Renesas Technology Corp – SuperH RISC engine

3.6.5 Data TLB Miss Exception
A data TLB miss exception occurs when address translation information for the virtual address to
which a data access is made is not found in the UTLB entries. The data TLB miss exception
processing carried out by hardware and software is shown below.
Hardware Processing: In the event of a data TLB miss exception, hardware carries out the
following processing:
1. Sets the VPN of the virtual address at which the exception occurred in PTEH.
2. Sets the virtual address at which the exception occurred in TEA.
3. Sets exception code H'040 in the case of a read, or H'060 in the case of a write, in EXPEVT
(OCBP, OCBWB: read; OCBI, MOVCA.L: write).
4. Sets the PC value indicating the address of the instruction at which the exception occurred in
SPC. If the exception occurred at a delay slot, sets the PC value indicating the address of the
delayed branch instruction in SPC.
5. Sets the SR contents at the time of the exception in SSR, and sets the R15 contents at the time
in SGR.
6. Sets the MD bit in SR to 1, and switches to privileged mode.
7. Sets the BL bit in SR to 1, and masks subsequent exception requests.
8. Sets the RB bit in SR to 1.
9. Branches to the address obtained by adding offset H'0000 0400 to the contents of VBR, and
starts the data TLB miss exception handling routine.
Software Processing (Data TLB Miss Exception Handling Routine): Software is responsible
for searching the external memory page table and assigning the necessary page table entry.
Software should carry out the following processing in order to find and assign the necessary page
table entry.
1. Write to PTEL the values of the PPN, PR, SZ, C, D, SH, V, and WT bits in the page table
entry recorded in the external memory address translation table. If necessary, the values of the
SA and TC bits should be written to PTEA.
2. When the entry to be replaced in entry replacement is specified by software, write that value to
URC in the MMUCR register. If URC is greater than URB at this time, the value should be
changed to an appropriate value after issuing an LDTLB instruction.
3. Execute the LDTLB instruction and write the contents of PTEH, PTEL, and PTEA to the
UTLB.
4. Finally, execute the exception handling return instruction (RTE), terminate the exception
handling routine, and return control to the normal flow. The RTE instruction should be issued
at least one instruction after the LDTLB instruction.
Rev. 3.0, 04/02, page 78 of 1064