HD6417751 Datasheet, PDF (683/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Bit 3—Receive Error Interrupt Enable (REIE): Enables or disables generation of receive-error
interrupt (ERI) and break interrupt (BRI) requests. The REIE bit setting is valid only when the
RIE bit is 0.
Bit 3: REIE
Description
0
Receive-error interrupt (ERI) and break interrupt (BRI) requests disabled*
(Initial value)
1
Receive-error interrupt (ERI) and break interrupt (BRI) requests enabled
Note: * Receive-error interrupt (ERI) and break interrupt (BRI) requests can be cleared by reading 1
from the ER, BRK, or ORER flag, then clearing the flag to 0, or by clearing the RIE and
REIE bits to 0. When REIE is set to 1, ERI and BRI interrupt requests will be generated
even if RIE is cleared to 0. In DMAC transfer, this setting is made if the interrupt controller is
to be notified of ERI and BRI interrupt requests.
Bits 1 and 0: Clock Enable 1 and 0 (CKE1 and CKE0): These bits select the SCIF clock source
and enable/disable clock output from the SCK2 pin. The combination of CKE1 and CKE0
determine whether the SCK2 pin functions as serial clock output pin or the serial clock input pin.
Note, however, that the setting of the CKE0 bit is valid only when CKE1 = 0 (internal clock
operation). When CKE1 = 1 (external clock), CKE0 is ignored. Also, be sure to set CKE1 and
CKE0 prior to determining the SCIF operating mode with SCSMR2.
Bit 1: CKE1
Bit 0: CKE0
Description
0
0
Internal clock/SCK pin functions as port (Initial value)
1
Internal clock/SCK2 pin functions as clock output*¹
1
0
External clock/SCK2 pin functions as clock input*²
1
External clock/SCK2 pin functions as clock input*²
Notes: *1 Outputs a clock with a frequency 16 times the bit rate.
*2 Inputs a clock with a frequency 16 times the bit rate.
Rev. 3.0, 04/02, page 643 of 1064