HD6417751 Datasheet, PDF (193/1105 Pages) Renesas Technology Corp – SuperH RISC engine

5.8 Restrictions
1. Restrictions on first instruction of exception handling routine
• Do not locate a BT, BF, BT/S, BF/S, BRA, or BSR instruction at address VBR + H'100, VBR
+ H'400, or VBR + H'600.
• When the UBDE bit in the BRCR register is set to 1 and the user break debug support
function* is used, do not locate a BT, BF, BT/S, BF/S, BRA, or BSR instruction at the address
indicated by the DBR register.
Note: * See section 20.4, User Break Debug Support Function.
Rev. 3.0, 04/02, page 153 of 1064