HD6417751 Datasheet, PDF (844/1105 Pages) Renesas Technology Corp – SuperH RISC engine

22.1.3 Pin Configuration
Table 22.1 shows the configuration of I/O pins of the PCIC.
Table 22.1 Pin Configuration
PCI
No.
Pin Name
Standard
Signal
Name
Function
I/O Pull-up
Type Resistor*¹
I/O Status
in Operating Modes
Host
Non-host
Remarks
Master Target Master Target
1 PCICLK CLK
PCI input clock
in
(33 MHz/66 MHz)
I
I
I
I
2 3&,567 —
Reset output
out
O
O
—
—
3 AD31 to AD[31:0] Address/data
t/s
AD0
I/O
I/O
I/O
I/O Low level
output at
reset
4 C/%( to C/%([3:0] Command/byte
t/s
C/%(
enable
O
I
O
I Low level
output at
reset
5 PAR
PAR
Parity
t/s
I/O
I/O
I/O
I/O Low level
output at
reset
6 3&,)5$0( )5$0( Bus cycle
s/t/s Yes
O
I
O
I
7 ,5'<
,5'<
Initiator ready
s/t/s Yes
O
I
O
I
8 75'<
75'< Target ready
s/t/s Yes
I
O
I
O
9 3&,6723 6723 Transaction stop s/t/s Yes
I
O
I
O
10 3&,/2&. /2&. Exclusive access s/t/s Yes
O
I
O
I
control
11 '(96(/ '(96(/ Device select
s/t/s Yes
I
O
I
O
12 3&,5(4/ 5(4 Bus request
t/s
Yes
I
I
—
—
*17,1
(host function)
*17
Bus grant
t/s
Yes
—
—
I
13 3&,*17/ *17 Bus grant
t/s
No
5(4287
(host function)
O
O
—
—
5(4
Bus request
t/s
No
—
—
O
14 3(55
3(55 Parity error
s/t/s Yes
I/O
O
I/O
O
15 6(55
6(55 System error
o/d
Yes
O
O
O
O
16 ,17$
,17$
Interrupt (async) o/d
Yes
—
—
O
O
17 3&,5(4/ 5(4 Bus request
t/s
Yes
I
I
—
—
MD9
(host function)
PCI clock switch in
(BCLK/PCICLK)
I
I
I
I
*²
Rev. 3.0, 04/02, page 804 of 1064