HD6417751 Datasheet, PDF (526/1105 Pages) Renesas Technology Corp – SuperH RISC engine

14.3.2 DMA Transfer Requests
DMA transfer requests are basically generated at either the data transfer source or destination, but
they can also be issued by external devices or on-chip peripheral modules that are neither the
source nor the destination.
Transfers can be requested in three modes: auto-request, external request, and on-chip peripheral
module request. The transfer request mode is selected by means of bits RS3–RS0 in DMA channel
control registers 0–3 (CHCR0–CHCR3).
Auto Request Mode: When there is no transfer request signal from an external source, as in a
memory-to-memory transfer or a transfer between memory and an on-chip peripheral module
unable to request a transfer, the auto-request mode allows the DMAC to automatically generate a
transfer request signal internally. When the DE bit in CHCR0–CHCR3 and the DME bit in the
DMA operation register (DMAOR) are set to 1, the transfer begins (so long as the TE bit in
CHCR0–CHCR3 and the NMIF and AE bits in DMAOR are all 0).
External Request Mode: In this mode a transfer is performed in response to a transfer request
signal ('5(4) from an external device. One of the modes shown in table 14.4 should be chosen
according to the application system. If DMA transfer is enabled (DE = 1, DME = 1, TE = 0, NMIF
= 0, AE = 0), transfer starts when '5(4 is input. The DS bit in CHCR0/CHCR1 is used to select
either falling edge detection or low level detection for the '5(4 signal (level detection when DS
= 0, edge detection when DS = 1).
'5(4 is accepted after a power-on reset if TE = 0, NMIF = 0, and AE = 0, but transfer is not
executed if DMA transfer is not enabled (DE = 0 or DME = 0).
In this case, DMA transfer is started when enabled (by setting DE = 1 and DME = 1).
The source of the transfer request does not have to be the data transfer source or destination.
Rev. 3.0, 04/02, page 486 of 1064