HD6417751 Datasheet, PDF (886/1105 Pages) Renesas Technology Corp – SuperH RISC engine

22.2.20 PCI Interrupt Register (PCIINT)
Bit: 31
30
29
28
27
26
25
24
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
PCI-R/W: R
R
R
R
R
R
R
R
PP Bus-R/W: R
R
R
R
R
R
R
R
Bit: 23
22
21
20
19
18
17
16
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
PCI-R/W: R
R
R
R
R
R
R
R
PP Bus-R/W: R
R
R
R
R
R
R
R
Bit: 15
14
13
12
11
10
9
8
M_LOCK T_TGT_A —
—
—
— TGT_RET MST_DIS
ON BORT
RY
Initial value: 0
0
0
0
0
0
0
0
PCI-R/W: R/WC R/WC
R
R
R
R
R/WC R/WC
PP Bus-R/W: R/WC R/WC
R
R
R
R
R/WC R/WC
Bit: 7
6
5
4
3
2
1
0
ADRPER SERR_D T_DPER T_PERR_ M_TGT_AM_MST_ M_DPER M_DPER
R
ET R_WT DET BORT ABORT R_WT R_RD
Initial value: 0
0
0
0
0
0
0
0
PCI-R/W: R/WC R/WC R/WC R/WC R/WC R/WC R/WC R/WC
PP Bus-R/W: R/WC R/WC R/WC R/WC R/WC R/WC R/WC R/WC
Note: WC: Cleared by writing “1”. (Writing of 0 is ignored.)
The PCI interrupt register (PCIINT) is a 32-bit register that saves the error source when an error
occurs on the PCI bus as a result of the PCIC attempting to invoke a transfer on the PCI bus, or
when the PCIC is the PCI master or PCI target. This register can be read from both the PP bus and
PCI bus. Also, 1 can be written from either the PP bus or PCI bus to perform a write-clear in
which the detection bit is cleared to its initial value (0).
The PCIINT register is initialized to H'00000000 at a power-on reset or software reset.
When an error occurs, the bit corresponding to the error content is set to 1. Each interrupt
detection bit can be cleared to its initial status (0) by writing 1 to it. (Write clear)
Rev. 3.0, 04/02, page 846 of 1064