HD6417751 Datasheet, PDF (803/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Bit 6—PC Break Select B (PCBB): Specifies whether a channel B instruction access cycle break
is to be effected before or after the instruction is executed. This bit is not initialized by a power-on
reset or manual reset.
Bit 6: PCBB
0
1
Description
Channel B PC break is effected before instruction execution
Channel B PC break is effected after instruction execution
Bits 5 and 4—Reserved: These bits are always read as 0, and should only be written with 0.
Bit 3—Sequence Condition Select (SEQ): Specifies whether the conditions for channels A and B
are to be independent or sequential. This bit is not initialized by a power-on reset or manual reset.
Bit 3: SEQ
0
1
Description
Channel A and B comparisons are performed as independent conditions
Channel A and B comparisons are performed as sequential conditions
(channel A → channel B)
Bits 2 and 1—Reserved: These bits are always read as 0, and should only be written with 0.
Bit 0—User Break Debug Enable (UBDE): Specifies whether the user break debug function (see
section 20.4, User Break Debug Support Function) is to be used.
Bit 0: UBDE
0
1
Description
User break debug function is not used
User break debug function is used
(Initial value)
20.3 Operation
20.3.1 Explanation of Terms Relating to Accesses
An instruction access is an access that obtains an instruction. For example, the fetching of an
instruction from the branch destination when a branch instruction is executed is an instruction
access. An operand access is any memory access for the purpose of instruction execution. For
example, the access to address PC+disp×2+4 in the instruction MOV.W@(disp,PC), Rn is an
operand access. As the term “data” is used to distinguish data from an address, the term “operand
access” is used in this section.
Rev. 3.0, 04/02, page 763 of 1064