HD6417751 Datasheet, PDF (388/1105 Pages) Renesas Technology Corp – SuperH RISC engine

BE
EDOMODE
8/16/32/64-Bit Transfer
32-Byte Transfer
0
0
Single
Single
1
Setting prohibited
Setting prohibited
1
0
Single/fast page*
Fast page
1
EDO
EDO
Note: * In fast page mode, 32-bit or 64-bit transfer with a 16-bit bus, 64-bit transfer with a 32-bit bus
Bits 8 and 7—Memory Data Size (SZ1, SZ0): These bits specify the bus width of DRAM and
synchronous DRAM. This setting has priority over the BCR2 register setting.
Bit 8: SZ1
0
1
Bit 7: SZ0
0
1
0
1
Description
DRAM
SDRAM
Reserved (Setting prohibited) Reserved (Setting prohibited)
Reserved (Setting prohibited) Reserved (Setting prohibited)
16 bits
Reserved (Setting prohibited)
32 bits
32 bits
Bits 6 to 3—Address Multiplexing (AMXEXT, AMX2–AMX0): These bits specify address
multiplexing for DRAM and synchronous DRAM. The address shift value is different for the
DRAM interface and the synchronous DRAM interface.
• For DRAM Interface:
Bit 6:
AMXEXT
Bit 5:
AMX2
Bit 4:
AMX1
Bit 3:
AMX0
Description
DRAM
0*
0
0
0
8-bit column address product
(Initial value)
1
9-bit column address product
1
0
10-bit column address product
1
11-bit column address product
1
0
0
12-bit column address product
1
Reserved (Setting prohibited)
1
0
Reserved (Setting prohibited)
1
Reserved (Setting prohibited)
Note: * When the DRAM interface is used, clear the AMXEXT bit to 0.
Rev. 3.0, 04/02, page 348 of 1064