HD6417751 Datasheet, PDF (290/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Bit 9—PLL Circuit 2 Enable (PLL2EN): Specifies whether PLL circuit 2 is on or off.
Bit 9: PLL2EN
0
1
Description
PLL circuit 2 is not used
PLL circuit 2 is used
(Initial value)
Bits 8 to 6—CPU Clock Frequency Division Ratio (IFC): These bits specify the CPU clock
frequency division ratio with respect to the input clock, 1/2 frequency divider, or PLL circuit 1
output frequency.
Bit 8: IFC2
0
Bit 7: IFC1
0
1
1
0
Other than the above
Bit 6: IFC0
0
1
0
1
0
1
Description
×1
× 1/2
× 1/3
× 1/4
× 1/6
× 1/8
Setting prohibited (Do not set)
Bits 5 to 3—Bus Clock Frequency Division Ratio (BFC): These bits specify the bus clock
frequency division ratio with respect to the input clock, 1/2 frequency divider, or PLL circuit 1
output frequency.
Bit 5: BFC2
0
Bit 4: BFC1
0
1
1
0
Other than the above
Bit 3: BFC0
0
1
0
1
0
1
Description
×1
× 1/2
× 1/3
× 1/4
× 1/6
× 1/8
Setting prohibited (Do not set)
Bits 2 to 0—Peripheral Module Clock Frequency Division Ratio (PFC): These bits specify the
peripheral module clock frequency division ratio with respect to the input clock, 1/2 frequency
divider, or PLL circuit 1 output frequency.
Rev. 3.0, 04/02, page 250 of 1064