HD6417751 Datasheet, PDF (563/1105 Pages) Renesas Technology Corp – SuperH RISC engine

• 7'$&.: Reply strobe signal for external device from DMAC
The assertion timing is the same as the DACKn assertion timing for each memory interface.
However, note that 7'$&. is an active-low signal.
• ID1, ID0: Channel number notification signals
 00: Channel 0
 01: Channel 1
 10: Channel 2
 11: Channel 3
Data Transfer Request Format (DTR)
31 28 27 25 23
SZ
ID MD
0
(Reserved)
(Reserved)
Figure 14.25 Data Transfer Request Format
The data transfer request format (DTR format) consists of 32 bits. In the case of normal data
transfer mode (channel 0, except channel 0) and the handshake protocol using the data bus,
channel number and transfer request mode are specified. Connection is made to D31 through D0.
Bits 31 to 29: Transmit Size (SZ2–SZ0)
• 000: Handshake protocol (data bus used)
• 001: Setting prohibited
• 010: Setting prohibited
• 011: Setting prohibited
• 100: Setting prohibited
• 101: Setting prohibited
• 110: Request queue clear specification
• 111: Transfer end specification
Bit 28: Reserved
Bits 27 and 26: Channel Number (ID1, ID0)
• 00: Channel 0
• 01: Channel 1
• 10: Channel 2
• 11: Channel 3
Rev. 3.0, 04/02, page 523 of 1064