HD6417751 Datasheet, PDF (521/1105 Pages) Renesas Technology Corp – SuperH RISC engine

14.2.5 DMA Operation Register (DMAOR)
Bit: 31
30
29
28
27
26
25
24
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit: 23
22
21
20
19
18
17
16
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit: 15
14
13
12
11
10
9
8
DDT
—
—
—
—
—
PR1
PR0
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W
R
R
R
R
R
R/W
R/W
Bit: 7
6
5
4
3
2
1
0
—
—
—
—
—
AE
NMIF DME
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R/(W) R/(W) R/W
Note: The AE and NMIF bits can only be written with 0 after being read as 1, to clear the flags.
DMAOR is a 32-bit readable/writable register that specifies the DMAC transfer mode.
DMAOR is initialized to H'00000000 by a power-on or manual reset. They retain their values in
standby mode and deep sleep mode.
Bits 31 to 16—Reserved: These bits are always read as 0, and should only be written with 0.
Bit 15—On-Demand Data Transfer (DDT): Specifies on-demand data transfer mode.
Bit 15: DDT
Description
0
Normal DMA mode
(Initial value)
1
On-demand data transfer mode
Note: %$9/ (DRAK0) is an active-high output in normal DMA mode. When the DDT bit is set to 1,
the %$9/ pin function is enabled and this pin becomes an active-low output.
Rev. 3.0, 04/02, page 481 of 1064