HD6417751 Datasheet, PDF (411/1105 Pages) Renesas Technology Corp – SuperH RISC engine

CKIO
A25–A0
RD/
D31–D0
(read)
D31–D0
(write)
T1
T2
DACKn
(SA: IO ← memory)
DACKn
(SA: IO → memory)
DACKn
(DA)
SA: Single address DMA
DA: Dual address DMA
Figure 13.6 Basic Timing of SRAM Interface
Rev. 3.0, 04/02, page 371 of 1064