HD6417751 Datasheet, PDF (486/1105 Pages) Renesas Technology Corp – SuperH RISC engine

CKIO
/
D31–D0
Tm1
Tmd1w Tmd1w
Tmd1
Tmd2
A
D0
D1
RD/
DACKn
(DA)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.63 MPX Interface Timing 4
(Burst Write Cycle, AnW = 1, One External Wait Inserted, Bus Width: 32 Bits,
Transfer Data Size: 64 Bits)
Rev. 3.0, 04/02, page 446 of 1064