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HD6417751 Datasheet, PDF (494/1105 Pages) Renesas Technology Corp – SuperH RISC engine | |||
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CKIO
A25âA0
T1
Tw
Twe
T2
RD/
D31âD0
(read)
DACKn
(SA: IO â memory)
DACKn
(DA)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.71 Byte Control SRAM Basic Read Cycle (One Internal Wait + One External
Wait)
Rev. 3.0, 04/02, page 454 of 1064
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