HD6417751 Datasheet, PDF (362/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Bit 14—High Impedance Control (HIZCNT): Specifies the state of the 5$6 and &$6 signals in
standby mode and when the bus is released.
Bit 14: HIZCNT
0
1
Description
The 5$6, :(Q, &$6Q/DQMn, and 5'/&$66/)5$0( signals go to high-
impedance (Hi-Z) in standby mode and when the bus is released
(Initial value)
The 5$6, :(Q, &$6Q/DQMn, and 5'/&$66/)5$0( signals drive in
standby mode and when the bus is released
Bits 13 to 11—Area 0 Burst ROM Control (A0BST2–A0BST0): These bits specify whether
burst ROM interface is used in area 0. When burst ROM interface is used, they also specify the
number of accesses in a burst. If area 0 is an MPX interface area, these bits are ignored.
Bit 13: A0BST2
0
1
Bit 12: A0BST1
0
1
0
1
Bit 11: A0BST0
0
1
0
1
0
1
0
1
Description
Area 0 is accessed as SRAM interface
(Initial value)
Area 0 is accessed as burst ROM
interface (4 consecutive accesses)
Can be used with 8-, 16-, or 32-bit bus
width
Area 0 is accessed as burst ROM
interface (8 consecutive accesses)
Can be used with 8-, 16-, or 32-bit bus
width
Area 0 is accessed as burst ROM
interface (16 consecutive accesses)
Can only be used with 8- or 16-bit bus
width. Do not specify for 32-bit bus width
Area 0 is accessed as burst ROM
interface (32 consecutive accesses)
Can only be used with 8-bit bus width
Reserved
Reserved
Reserved
Rev. 3.0, 04/02, page 322 of 1064