HD6417751 Datasheet, PDF (397/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: —
—
—
—
—
—
—
—
Bit: 7
6
5
4
3
2
1
0
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
13.2.13 Refresh Time Constant Register (RTCOR)
The refresh time constant register (RTCOR) is a readable/writable register that specifies the upper
limit of the RTCNT counter. The RTCOR register and RTCNT counter values (lower 8 bits) are
constantly compared, and when they match the CMF bit is set in the RTCSR register and the
RTCNT counter is cleared to 0. If the refresh bit (RFSH) has been set to 1 in the memory control
register (MCR) and CAS-before-RAS has been selected as the refresh mode, a memory refresh
cycle is generated when the CMF bit is set.
RTCOR is initialized to H'0000 by a power-on reset, but is not initialized, and retains its contents,
in a manual reset and in standby mode.
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: —
—
—
—
—
—
—
—
Bit: 7
6
5
4
3
2
1
0
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Rev. 3.0, 04/02, page 357 of 1064