HD6417751 Datasheet, PDF (28/1105 Pages) Renesas Technology Corp – SuperH RISC engine

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Write to Synchronous DRAM (Row Hit) ...................................................... 536
Single Address Mode/Burst Mode/External Bus → External Device 32-Byte
Block Transfer/Channel 0 On-Demand Data Transfer ................................... 537
DDT Mode Setting....................................................................................... 538
Single Address Mode/Burst Mode/Edge Detection/ External Device →
External Bus Data Transfer........................................................................... 538
Single Address Mode/Burst Mode/Level Detection/ External Bus → External
Device Data Transfer ................................................................................... 539
Single Address Mode/Burst Mode/Edge Detection/Byte, Word, Longword,
Quadword/External Bus → External Device Data Transfer ........................... 539
Single Address Mode/Burst Mode/Edge Detection/Byte, Word, Longword,
Quadword/External Device → External Bus Data Transfer ........................... 540
Single Address Mode/Burst Mode/32-Byte Block Transfer/DMA Transfer
Request to Channels 1–3 Using Data Bus ..................................................... 541
Single Address Mode/Burst Mode/32-Byte Block Transfer/ External Bus →
External Device Data Transfer/ Direct Data Transfer Request to Channel 2
without Using Data Bus................................................................................ 542
Single Address Mode/Burst Mode/External Bus → External Device Data
Transfer/Direct Data Transfer Request to Channel 2 ..................................... 543
Single Address Mode/Burst Mode/External Device → External Bus Data
Transfer/Direct Data Transfer Request to Channel 2 ..................................... 544
Single Address Mode/Burst Mode/External Bus → External Device Data
Transfer (Active Bank Address)/Direct Data Transfer Request to Channel 2.. 545
Single Address Mode/Burst Mode/External Device → External Bus Data
Transfer (Active Bank Address)/Direct Data Transfer Request to Channel 2.. 546
Block Diagram of the DMAC....................................................................... 550
DTR Format (Transfer Request Format) (SH7751R)..................................... 560
Single Address Mode/Burst Mode/External Bus → External Device 32-Byte
Block Transfer/Channel 0 On-Demand Data Transfer ................................... 565
Single Address Mode/Cycle Steal Mode/External Bus → External Device/
32-Byte Block Transfer/On-Demand Data Transfer on Channel 4 ................. 566
Block Diagram of SCI.................................................................................. 571
SCK Pin....................................................................................................... 587
TxD Pin ....................................................................................................... 588
RxD Pin....................................................................................................... 588
Data Format in Asynchronous Communication (Example with 8-Bit Data,
Parity, Two Stop Bits) .................................................................................. 599
Relation between Output Clock and Transfer Data Phase
(Asynchronous Mode).................................................................................. 601
Sample SCI Initialization Flowchart ............................................................. 602
Sample Serial Transmission Flowchart ......................................................... 603
Example of Transmit Operation in Asynchronous Mode
(Example with 8-Bit Data, Parity, One Stop Bit) ........................................... 605
Rev. 3.0, 04/02, page xxvi of xxxviii