HD6417751 Datasheet, PDF (1019/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Figure 23.24 Synchronous DRAM Normal Read Bus Cycle: PRE + ACT + READ
Commands, Burst (RCD [1:0] = 01, TPC [2:0] = 001, CAS Latency = 3)
Rev. 3.0, 04/02, page 979 of 1064