HD6417751 Datasheet, PDF (455/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Synchronous DRAM mode register setting should be executed once only after power-on reset and
before synchronous DRAM access, and no subsequent changes should be made.
CKIO
TRp1 TRp2 TRp3 TRp4 TMw1 TMw2 TMw3 TMw4 TMw5
Bank
Precharge-sel
Address
RD/
D31–D0
CKE
(High)
Figure 13.38(1) Synchronous DRAM Mode Write Timing (PALL)
Rev. 3.0, 04/02, page 415 of 1064