HD6417751 Datasheet, PDF (17/1105 Pages) Renesas Technology Corp – SuperH RISC engine

17.3.1 Overview......................................................................................................... 686
17.3.2 Pin Connections............................................................................................... 687
17.3.3 Data Format .................................................................................................... 688
17.3.4 Register Settings.............................................................................................. 689
17.3.5 Clock .............................................................................................................. 691
17.3.6 Data Transfer Operations ................................................................................. 694
17.4 Usage Notes................................................................................................................. 701
Section 18 I/O Ports ....................................................................................................... 707
18.1 Overview ..................................................................................................................... 707
18.1.1 Features........................................................................................................... 707
18.1.2 Block Diagrams............................................................................................... 708
18.1.3 Pin Configuration ............................................................................................ 715
18.1.4 Register Configuration..................................................................................... 718
18.2 Register Descriptions ................................................................................................... 719
18.2.1 Port Control Register A (PCTRA).................................................................... 719
18.2.2 Port Data Register A (PDTRA)........................................................................ 720
18.2.3 Port Control Register B (PCTRB) .................................................................... 720
18.2.4 Port Data Register B (PDTRB) ........................................................................ 722
18.2.5 GPIO Interrupt Control Register (GPIOIC) ...................................................... 722
18.2.6 Serial Port Register (SCSPTR1)....................................................................... 723
18.2.7 Serial Port Register (SCSPTR2)....................................................................... 725
Section 19 Interrupt Controller (INTC) ..................................................................... 729
19.1 Overview ..................................................................................................................... 729
19.1.1 Features........................................................................................................... 729
19.1.2 Block Diagram ................................................................................................ 729
19.1.3 Pin Configuration ............................................................................................ 731
19.1.4 Register Configuration..................................................................................... 731
19.2 Interrupt Sources.......................................................................................................... 732
19.2.1 NMI Interrupt .................................................................................................. 732
19.2.2 IRL Interrupts.................................................................................................. 733
19.2.3 On-Chip Peripheral Module Interrupts ............................................................. 735
19.2.4 Interrupt Exception Handling and Priority........................................................ 736
19.3 Register Descriptions ................................................................................................... 739
19.3.1 Interrupt Priority Registers A to D (IPRA–IPRD)............................................. 739
19.3.2 Interrupt Control Register (ICR) ...................................................................... 740
19.3.3 Interrupt Priority Level Settting Register 00 (INTPRI00).................................. 742
19.3.4 Interrupt Factor Register 00 (INTREQ00) ........................................................ 743
19.3.5 Interrupt Mask Register 00 (INTMSK00)......................................................... 744
19.3.6 Interrupt Mask Clear Register 00 (INTMSKCLR00) ........................................ 745
19.3.7 INTREQ00, INTMSK00, and INTMSKCLR00 bit allocation........................... 746
19.4 INTC Operation ........................................................................................................... 747
Rev. 3.0, 04/02, page xv of xxxviii