HD6417751 Datasheet, PDF (8/1105 Pages) Renesas Technology Corp – SuperH RISC engine

3.4.2 Instruction TLB (ITLB) Configuration............................................................. 69
3.4.3 Address Translation Method ............................................................................ 69
3.5 MMU Functions .......................................................................................................... 72
3.5.1 MMU Hardware Management ......................................................................... 72
3.5.2 MMU Software Management........................................................................... 72
3.5.3 MMU Instruction (LDTLB)............................................................................. 72
3.5.4 Hardware ITLB Miss Handling........................................................................ 73
3.5.5 Avoiding Synonym Problems .......................................................................... 74
3.6 MMU Exceptions......................................................................................................... 75
3.6.1 Instruction TLB Multiple Hit Exception........................................................... 75
3.6.2 Instruction TLB Miss Exception ...................................................................... 75
3.6.3 Instruction TLB Protection Violation Exception............................................... 76
3.6.4 Data TLB Multiple Hit Exception .................................................................... 77
3.6.5 Data TLB Miss Exception ............................................................................... 78
3.6.6 Data TLB Protection Violation Exception ........................................................ 79
3.6.7 Initial Page Write Exception ............................................................................ 79
3.7 Memory-Mapped TLB Configuration........................................................................... 80
3.7.1 ITLB Address Array........................................................................................ 81
3.7.2 ITLB Data Array 1 .......................................................................................... 82
3.7.3 ITLB Data Array 2 .......................................................................................... 83
3.7.4 UTLB Address Array ...................................................................................... 83
3.7.5 UTLB Data Array 1......................................................................................... 85
3.7.6 UTLB Data Array 2......................................................................................... 86
Section 4 Caches .......................................................................................................... 87
4.1 Overview..................................................................................................................... 87
4.1.1 Features........................................................................................................... 87
4.1.2 Register Configuration..................................................................................... 88
4.2 Register Descriptions ................................................................................................... 89
4.3 Operand Cache (OC).................................................................................................... 91
4.3.1 Configuration .................................................................................................. 91
4.3.2 Read Operation ............................................................................................... 94
4.3.3 Write Operation............................................................................................... 95
4.3.4 Write-Back Buffer........................................................................................... 97
4.3.5 Write-Through Buffer...................................................................................... 97
4.3.6 RAM Mode ..................................................................................................... 97
4.3.7 OC Index Mode............................................................................................... 99
4.3.8 Coherency between Cache and External Memory............................................. 99
4.3.9 Prefetch Operation........................................................................................... 99
4.4 Instruction Cache (IC).................................................................................................. 99
4.4.1 Configuration .................................................................................................. 99
4.4.2 Read Operation ............................................................................................... 102
4.4.3 IC Index Mode ................................................................................................ 102
Rev. 3.0, 04/02, page vi of xxxviii