HD6417751 Datasheet, PDF (852/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Bits 31 to 16—DEVID15 to 0: These bits specify the device ID of the SH7751 or SH7751R
allocated by the PCI device vendor. H'3505 (fixed in hardware) for the SH7751, and H'350E
(fixed in hardware) for the SH7751R.
Bits 15 to 0—DNVID15 to 0: These bits specify Hitachi as the PCI device maker (vendor ID).
(H'1054: fixed in hardware)
22.2.2 PCI Configuration Register 1 (PCICONF1)
Bit:
Initial value:
PCI-R/W:
PP Bus-R/W:
31
DPE
0
R/WC
R/WC
30
SSE
0
R/WC
R/WC
29
RMA
0
R/WC
R/WC
28
RTA
0
R/WC
R/WC
27
STA
0
R/WC
R/WC
26
DEV1
0
R
R
25
DEV0
1
R
R
24
DPD
0
R/WC
R/WC
Bit: 23
22
21
20
19
18
17
16
FBBC UDF
66M
PM
—
—
—
—
Initial value: 1
0
0
1
0
0
0
0
PCI-R/W: R
R
R
R
R
R
R
R
PP Bus-R/W: R
R/W
R/W
R
R
R
R
R
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
PBBE SER
Initial value: 0
0
0
0
0
0
0
0
PCI-R/W: R
R
R
R
R
R
R
R/W
PP Bus-R/W: R
R
R
R
R
R
R
R/W
Bit: 7
6
5
4
3
2
1
0
WCC PER
VPS MWIE SPC
BUM
MES
IOS
Initial value: 1
0
0
0
0
0
0
0
PCI-R/W: R/W
R/W
R
R
R
R/W
R/W
R/W
PP Bus-R/W: R/W
R/W
R
R
R
R/W
R/W
R/W
Note: Cleared by writing WC:1. (Writing of 0 is ignored.)
PCI configuration register 1 (PCICONF1) is a 32-bit read/partial-write register that includes the
status and command PCI configuration registers stipulated in the PCI local bus specifications. The
status is read from bits 31 to 16 (status register) in the event of an error on the PCI bus. Bits 15 to
0 (command register) contain the settings required for initiating transfers on the PCI bus.
Rev. 3.0, 04/02, page 812 of 1064