HD6417751 Datasheet, PDF (679/1105 Pages) Renesas Technology Corp – SuperH RISC engine

16.2.5 Serial Mode Register (SCSMR2)
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit: 7
—
Initial value: 0
R/W: R
6
5
4
3
2
CHR
PE
O/ STOP
—
0
0
0
0
0
R/W
R/W
R/W
R/W
R
1
CKS1
0
R/W
0
CKS0
0
R/W
SCSMR2 is a 16-bit register used to set the SCIF’s serial transfer format and select the baud rate
generator clock source.
SCSMR2 can be read or written to by the CPU at all times.
SCSMR2 is initialized to H'0000 by a power-on reset or manual reset. It is not initialized in
standby mode or in the module standby state.
Bits 15 to 7—Reserved: These bits are always read as 0, and should only be written with 0.
Bit 6—Character Length (CHR): Selects 7 or 8 bits as the asynchronous mode data length.
Bit 6: CHR
Description
0
8-bit data
(Initial value)
1
7-bit data*
Note: * When 7-bit data is selected, the MSB (bit 7) of SCFTDR2 is not transmitted.
Bit 5—Parity Enable (PE): Selects whether or not parity bit addition is performed in
transmission, and parity bit checking in reception.
Bit 5: PE
Description
0
Parity bit addition and checking disabled
(Initial value)
1
Parity bit addition and checking enabled*
Note: * When the PE bit is set to 1, the parity (even or odd) specified by the O/ bit is added to
transmit data before transmission. In reception, the parity bit is checked for the parity (even
or odd) specified by the O/ bit.
Bit 4—Parity Mode (O/): Selects either even or odd parity for use in parity addition and
checking. The O/ bit setting is only valid when the PE bit is set to 1, enabling parity bit addition
and checking. The O/ bit setting is invalid when parity addition and checking is disabled.
Rev. 3.0, 04/02, page 639 of 1064