HD6417751 Datasheet, PDF (931/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Notes: *1 In the SH7751, this is not compliant with version 2.1 of the PCI specifications, in
which the I/O space for PCI devices is defined as being no more than 256 bytes. When
the SH7751 is used in a PCI non-host device, such as on a PCI card, it may be
recognized as a device that cannot be used during device configuration, because it
requires an I/O space that is larger than 256 bytes.
*2 In the SH7751, this is not compliant with version 2.1 of the PCI specifications, which
states that any combination of the byte-enable signals (%( [3:0]) is possible when
accepting a configuration access. For this reason, when access in units of bytes or
words is specified by the combination of %( [3:0], the whole longword unit is
overwritten by the write operation.
Locked Transfer: Locked transfers are supported, but the locked space becomes the whole
memory of the PCIC in the case of memory transfers, and becomes the whole register space in the
case of I/O transfers or configuration transfers. While the memory is locked, retry is returned for
all memory accesses of the PCIC from other PCI devices. Register access is, however, accepted.
Similarly, while the registers are locked, retry is returned for all I/O accesses or configuration
accesses of the PCIC from another PCI device, but memory access is accepted.
22.3.9 DMA Transfers
DMA transfers allow the high-speed transfer of data between devices connected to the local bus
and PCI bus when the PCIC has bus privileges as master. The following commands are supported
in the case of DMA transfers:
• Memory read, memory write, I/O read, and I/O write
(Locked transfers are not supported.)
(High-speed back-to-back transfers are not supported.)
There are four DMA channels. In each channel, a maximum of 64MB can be set for each transfer,
the number of transfer bytes and the starting address for the transfer being set at a longword
boundary.
In DMA transfers, all transferred data is handled in long word units, so the number of transfer
bytes and the low 2 bits of the transfer initial address are ignored and B'0000 is always output for
%(>@. Also, in DMA transfers, because burst transfers are effected using linear addressing, the
low 2 bits of the output PCI address are always B'00.
Note that locked transfers are not supported in the case of DMA transfers.
Rev. 3.0, 04/02, page 891 of 1064