HD6417751 Datasheet, PDF (701/1105 Pages) Renesas Technology Corp – SuperH RISC engine

MD0/SCK2
Mode setting
register
Reset
R
QD
SCKIO
C
SPTRW
Reset
QR _D
SCKDT
C
SPTRW
Internal data bus
SCIF
Clock output enable signal
Serial clock output signal _*
Serial clock input signal
Clock input enable signal
SPTRR
SPTRW: Write to SPTR
SPTRR: Read SPTR
Note: * Signals that set the SCK2 pin function as internal clock output or external clock input according to
the CKE0 and CKE1 bits in SCSCR2.
Figure 16.6 MD0/SCK2 Pin
Rev. 3.0, 04/02, page 661 of 1064