HD6417751 Datasheet, PDF (564/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Bits 25 and 24: Transfer Request Mode (MD1, MD0)
• 00: Handshake protocol (data bus used)
• 01: Setting prohibited
• 10: Request queue clear specification
• 11: Setting prohibited
Bits 23 to 0: Reserved
Notes: 1. In channels 1 to 3, only the ID field is valid.
2. In channel 0, the MD field is valid. Set MD = 00. If 01, 10, or 11 is set, the DMAC
will halt with an address error.
3. In edge-sense burst mode, DMA transfer is executed continuously. In level-sense burst
mode and cycle steal mode, a handshake protocol is used to transfer each unit of data.
4. When specifying data transfer requests using a handshake protocol for channel 0, set
ID = 00, MD = 00, and SZ ≠ 101, 110 for the DTR format. Use the MOV instruction
to make settings in the DMAC's SAR0, DAR0, CHCR0, and DMATCR0 registers.
Either single address mode or dual address mode can be used as the transfer mode.
Select one of the following settings: CHCR0.RS3—RS0 = 0000, 0010, 0011.
Operation is not guaranteed if the DTR format data settings are DTR.ID = 00,
DTR.MD = 00, and DTR.SZ ≠ 101, 110.
Usable SZ, ID, and MD Combination in DDT Mode
Table 14.11 shows the usable combination of SZ, ID, and MD in DDT mode of the SH7751.
Table 14.11 Usable SZ, ID, and MD Combination in DDT Mode
SZ [2:0]
000
ID [1:0]
00
MD [1:0]
00
110
00
10
111
00
00
X
01
X
X
10
X
X
11
X
Notes: Don’t set values other than those shown in the above table.
X: Don’t care
Function
Request for transfer to
channel 0
Request queue clear
Transfer end
Request for transfer to
channel 1
Request for transfer to
channel 2
Request for transfer to
channel 3
Rev. 3.0, 04/02, page 524 of 1064