HD6417751 Datasheet, PDF (465/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Table 13.17 Relationship between Address and CE When Using PCMCIA Interface (cont)
Bus
Width
(Bits)
Access
Read/ Size Odd/
Write (Bits)*¹ Even
IOIS16 Access CE2 CE1 A0
D15–D8
D7–D0
Dynamic Read 8
Even 0
—
1 0 0 Invalid
Read data
bus
sizing*²
Odd 0
—
0 1 1 Read data
Invalid
16
Even 0
—
0 0 0 Upper read data Lower read data
Odd 0
—
————
—
Write 8
Even 0
—
1 0 0 Invalid
Write data
Odd 0
—
0 1 1 Write data
Invalid
16
Even 0
—
0 0 0 Upper write data Lower write data
Odd 0
—
————
—
Read 8
Even 1
—
1 0 0 Invalid
Read data
Odd 1
First 0 1 1 Ignored
Invalid
Odd 1
Second 1 0 1 Invalid
Read data
16
Even 1
First 0 0 0 Invalid
Lower read data
Even 1
Second 1 0 1 Invalid
Upper read data
Odd 1
—
————
—
Write 8
Even 1
—
1 0 0 Invalid
Write data
Odd 1
First 0 1 1 Invalid
Write data
Odd 1
Second 1 0 1 Invalid
Write data
16
Even 1
First 0 0 0 Upper write data Lower write data
Even 1
Second 1 0 1 Invalid
Upper write data
Odd 1
—
————
—
Notes: *1 In 32-bit/64-bit/32-byte transfer, the above accesses are repeated, with address
incrementing performed automatically according to the bus width, until the transfer data
size is reached.
*2 PCMCIA I/O card interface only
Rev. 3.0, 04/02, page 425 of 1064