HD6417751 Datasheet, PDF (400/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Data Configuration
MSB
LSB
Byte
Data 7–0
MSB
Word
Data 15–8
LSB
Data 7–0
MSB
Longword
Data 31–24
Data 23–16
Data 15–8
LSB
Data 7–0
MSB
Quadword
Data
63–56
Data
55–48
Data
47–40
Data
39–32
Data
31–24
Data
23–16
Data
15–8
LSB
Data
7–0
Table 13.8 32-Bit External Device/Big-Endian Access and Data Alignment
Operation
Data Bus
Access
Size Address No. D31–D24 D23–D16 D15–D8 D7–D0
Byte 4n
1 Data
—
7–0
—
—
4n+1 1 —
Data
—
—
7–0
4n+2 1 —
—
Data
—
7–0
4n+3 1 —
—
—
Data
7–0
Word 4n
1 Data
Data
—
—
15–8
7–0
4n+2 1 —
—
Data
Data
15–8 7–0
Long- 4n
word
1 Data
31–24
Data
23–16
Data
15–8
Data
7–0
Quad- 8n
word
1 Data
63–56
Data
55–48
Data
Data
47–40 39–32
8n+4
2 Data
31–24
Data
23–16
Data
15–8
Data
7–0
Strobe Signals
:(,
&$6,
DQM3
:(,
&$6,
DQM2
:(,
&$6,
DQM1
:(,
&$6,
DQM0
Asserted
Asserted
Asserted
Asserted
Asserted Asserted
Asserted Asserted
Asserted Asserted Asserted Asserted
Asserted Asserted Asserted Asserted
Asserted Asserted Asserted Asserted
Rev. 3.0, 04/02, page 360 of 1064