HD6417751 Datasheet, PDF (966/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Table 22.14 Method of Stopping Clock per Operating Mode (cont)
Transition/ Standby
Recovery
SH (Other
than PCIC)
Transition Standby
command
PCIC
Master
PCICLK BCLK
Operation Operation
Standby
command
PCICLK
stopped from
SH + standby
command
Recovery Not used
1
PME
interrupt
(connected
to IRL)
PME interrupt
(connected to
IRL) + PCICLK
restarted from
SH
Recovery
2
NMI, IRL,
and
RESET
on-chip
peripheral
interrupt
NMI, IRL,
and RESET
NMI, IRL,
RESET +
PCICLK
restarted from
SH
Notes: Recovery 1: Recovery from PCI bus
Recovery 2: Recovery from other than PCI bus
Slave
PCICLK
Operation
PCI command
+ interrupt
(PCIC → SH) +
standby
command
Power-on reset
NMI, IRL,
RESET + wait
for PCI
command
(recovery)
External Input Pin (PCICLK) Operating Mode: The PCI bus clock can be stopped by writing 1
to the PCICLKSTOP bit. The bus clock can be stopped by writing 1 to the BCLKSTOP bit. It
requires a minimum of 2 clocks of the PCI bus clock for the clock to actually stop after writing to
PCICLKR (setting the PCICLKSTOP bit to 1). It takes a similar time for the clock to restart.
Bus Clock (CKIO) Operating Mode: Both the PCI bus clock and bus clock can be stopped by
writing 1 to the BCLKSTOP bit. It requires a minimum of 2 clocks of the bus clock for the clock
to actually stop after writing to PCICLKR (setting the BCLKSTOP bit to 1). It takes a similar time
for the clock to restart.
While the PCI bus clock is stopped, it is not possible to access the local registers that can be
accessed both from the peripheral module internal bus and from the PCI bus. Neither writing nor
reading can be performed correctly.
Also, the following cautions must be observed when stopping the bus clock and PCI bus clock
while the PCI is in use:
Rev. 3.0, 04/02, page 926 of 1064