HD6417751 Datasheet, PDF (536/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Dual Address Mode: Dual address mode is used to access both the transfer source and the
transfer destination by address. The transfer source and destination can be accessed by either on-
chip peripheral module or external address.
In dual address mode, data is read from the transfer source in the data read cycle, and written to
the transfer destination in the data write cycle, so that the transfer is executed in two bus cycles.
The transfer data is temporarily stored in the data buffer in the bus state controller (BSC).
In a transfer between external memories such as that shown in figure 14.7, data is read from
external memory into the BSC’s data buffer in the read cycle, then written to the other external
memory in the write cycle. Figure 14.8 shows the timing for this operation.
DMAC
SAR
DAR
Memory
Transfer source
module
BSC ^{Data buffer}
Transfer destination
module
Taking the SAR value as the address, data is read from the transfer source module
and stored temporarily in the data buffer in the bus state controller (BSC).
1st bus cycle
DMAC
SAR
DAR
Memory
Transfer source
module
BSC Data buffer
Transfer destination
module
Taking the DAR value as the address, the data stored in the BSC’s data buffer is
written to the transfer destination module.
2nd bus cycle
Figure 14.7 Operation in Dual Address Mode
Rev. 3.0, 04/02, page 496 of 1064