HD6417751 Datasheet, PDF (918/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Bit 0—Port 0 Input/Output Data (PB0DT): Receives input data and sets output data when the
3&,5(4 pin is used as a port.
22.2.41 PIO Data Register (PCIPDR)
Bit: 31
30
29
28
27
26
25
24
PPDA31 PPDA30 PPDA29 PPDA28 PPDA27 PPDA26 PPDA25 PPDA24
Initial value: —
—
—
—
—
—
—
—
PCI-R/W: —
—
—
—
—
—
—
—
PP Bus-R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit: 23
22
21
20
19
18
17
16
PPDA23 PPDA22 PPDA21 PPDA20 PPDA19 PPDA18 PPDA17 PPDA16
Initial value: —
—
—
—
—
—
—
—
PCI-R/W: —
—
—
—
—
—
—
—
PP Bus-R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit: 15
14
13
12
11
10
9
PPDA15 PPDA14 PPDA13 PPDA12 PPDA11 PPDA10 PPDA9
Initial value: —
—
—
—
—
—
—
PCI-R/W: —
—
—
—
—
—
—
PP Bus-R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
8
PPDA8
—
—
R/W
Bit:
Initial value:
PCI-R/W:
PP Bus-R/W:
7
PPDA7
—
—
R/W
6
PPDA6
—
—
R/W
5
PPDA5
—
—
R/W
4
PPDA4
—
—
R/W
3
PPDA3
—
—
R/W
2
PPDA2
—
—
R/W
1
PPDA1
—
—
R/W
0
PPDA0
—
—
R/W
The PIO data register (PCIPDR) sets the data for read/write in the PCI configuration cycle. This
32-bit read/write register can be accessed from the PP bus.
The PCIPDR register is not initialized at a power-on reset or software reset. The initial value is
undefined.
Always write to this register before accessing the PCI configuration space. Always read/write to
this register after setting the value in the PIO address register (PIOPAR).
The configuration cycle on the PCI bus can be generated by reading/writing to this register.
Rev. 3.0, 04/02, page 878 of 1064