HD6417751 Datasheet, PDF (770/1105 Pages) Renesas Technology Corp – SuperH RISC engine

NMI
IRL3–
IRL0
Input control
4
4
TMU
RTC
SCI
SCIF
WDT
REF
DMAC
H-UDI
GPIO
PCIC
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
Priority
identifier
IPR
ICR
IPRA–IPRD,
INTPRI00
Com-
parator
Interrupt
request
SR
I3 I2 I1 I0
CPU
Bus interface
TMU:
Timer unit
RTC:
Realtime clock unit
SCI:
Serial communication interface
SCIF:
Serial communication interface with FIFO
WDT:
Watchdog timer
REF:
Memory refresh controller section of the bus state controller
DMAC:
Direct memory access controller
H-UDI:
Hitachi user debug interface unit
GPIO:
I/O port
PCIC:
PCI bus controller
ICR:
Interrupt control register
IPRA–IPRD: Interrupt priority registers A–D
INTPRI00: Interrupt priority register 00
SR:
Status register
INTC
Figure 19.1 Block Diagram of INTC
Rev. 3.0, 04/02, page 730 of 1064