HD6417751 Datasheet, PDF (822/1105 Pages) Renesas Technology Corp – SuperH RISC engine

21.2.2 Data Register (SDDR)
The data register (SDDR) is a 32-bit register, comprising the two 16-bit registers SDDRH and
SDDRL, that can be read and written to by the CPU. The value in this register is initialized by
7567, but not by a CPU reset.
Bit: 31
30
29
28
27
26
25
24
Initial value:
*
*
*
*
*
*
*
*
R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit: 23
22
21
20
19
18
17
16
Initial value:
*
*
*
*
*
*
*
*
R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit: 15
14
13
12
11
10
9
8
Initial value:
*
*
*
*
*
*
*
*
R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit: 7
6
5
4
3
2
1
0
Initial value:
*
*
*
*
*
*
*
*
R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note: *: Undefined
Bits 31 to 0—DR Data: These bits store the SDDR value.
21.2.3 Bypass Register (SDBPR)
The bypass register (SDBPR) is a one-bit register that cannot be accessed by the CPU. When
bypass mode is set in SDIR, SDBPR is connected between the TDI pin and TDO pin of the
H-UDI.
Rev. 3.0, 04/02, page 782 of 1064