HD6417751 Datasheet, PDF (654/1105 Pages) Renesas Technology Corp – SuperH RISC engine

1
Serial
data
Start
bit
Data
Multi-
proces- Stop
sor bit bit
0 D0 D1
D7 1 1
Start
bit
Data
Multi-
proces- Stop Start
sor bit bit bit
Multi-
Data proces- Stop
sor bit bit
1
0 D0 D1
D7 0 1 0 D0 D1
D7 0 ^{Idle state}
(mark state)
TDRE
TEND
One frame
Data written to SCTDR1
and TDRE flag cleared
to 0 by TXI interrupt
handler
MPBT bit cleared to 0, data
written to SCTDR1, and
TDRE flag cleared to 0 by
TEI interrupt handler
TXI interrupt
request
TEI interrupt
request
Figure 15.14 Example of SCI Transmit Operation (Example with 8-Bit Data,
Multiprocessor Bit, One Stop Bit)
Multiprocessor Serial Data Reception: Figure 15.15 shows a sample flowchart for
multiprocessor serial reception.
Use the following procedure for multiprocessor serial data reception after enabling the SCI for
reception.
Rev. 3.0, 04/02, page 614 of 1064