HD6417751 Datasheet, PDF (164/1105 Pages) Renesas Technology Corp – SuperH RISC engine

Table 5.2 Exceptions (cont)
Exception Execution
Category Mode
Exception
Priority Priority Vector
Level Order Address
Exception
Offset Code
Interrupt Completion Peripheral H-UDI H-UDI
4
type
module _{GPIO GPIOI}
interrupt
(module/ ^{DMAC DMTE0}
source)
DMTE1
*2
(VBR)
H'600
H'600
H'620
H'640
H'660
DMTE2
H'680
DMTE3
H'6A0
DMTE4*³
H'780
DMTE5*³
H'7A0
DMTE6*³
H'7C0
DMTE7*³
H'7E0
DMAE
H'6C0
SCIF ERI
H'700
RXI
H'720
BRI
H'740
TXI
H'760
PCIC(0) PCISERR
H'A00
PCIC(1) PCIERR
H'AE0
PCIPWDWN
H'AC0
PCIPWON
H'AA0
PCIDMA0
H'A80
PCIDMA1
H'A60
PCIDMA2
H'A40
PCIDMA3
H'A20
Priority: Priority is first assigned by priority level, then by priority order within each level (the lowest
number represents the highest priority).
Exception transition destination: Control passes to H'A000 0000 in a reset, and to [VBR + offset] in
other cases.
Exception code: Stored in EXPEVT for a reset or general exception, and in INTEVT for an interrupt.
IRL: Interrupt request level (pins IRL3–IRL0).
Module/source: See the sections on the relevant peripheral modules.
Notes: *1 When BRCR.UBDE = 1, PC = DBR. In other cases, PC = VBR + H'100.
*2 The priority order of external interrupts and peripheral module interrupts can be set by
software.
*3 SH7751R only
Rev. 3.0, 04/02, page 124 of 1064