HD6417751 Datasheet, PDF (414/1105 Pages) Renesas Technology Corp – SuperH RISC engine

SH7751 Series
A16
A0
D7
D0
128k × 8-bit
SRAM
A16
A0
I/O7
I/O0
Figure 13.9 Example of 8-Bit Data Width SRAM Connection
Wait State Control: Wait state insertion on the SRAM interface can be controlled by the WCR2
settings. If the WCR2 wait specification bits corresponding to a particular area are not zero, a
software wait is inserted in accordance with that specification. For details, see section 13.2.5, Wait
Control Register 2 (WCR2).
The specified number of Tw cycles are inserted as wait cycles using the SRAM interface wait
timing shown in figure 13.10.
Rev. 3.0, 04/02, page 374 of 1064