HD6417751 Datasheet, PDF (372/1105 Pages) Renesas Technology Corp – SuperH RISC engine

same device. The DMAIW bits are valid only for DMA single address transfer; with DMA dual
address transfer, inter-area idle cycles are inserted.
Bits 4n + 2 to 4n—Area n (6 to 0) Inter-Cycle Idle Specification (AnlW2–AnlW0): These bits
specify the number of idle cycles between bus cycles to be inserted when switching from external
memory space area n (n = 6 to 0) to another space, or from a read access to a write access in the
same space.
DMAIW2/AnIW2
0
1
DMAIW1/AnIW1
0
1
0
1
DMAIW0/AnIW0
0
1
0
1
0
1
0
1
Inserted Idle Cycles
0
1
2
3
6
9
12
15
(Initial value)
Rev. 3.0, 04/02, page 332 of 1064