HD6417751 Datasheet, PDF (681/1105 Pages) Renesas Technology Corp – SuperH RISC engine

16.2.6 Serial Control Register (SCSCR2)
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit: 7
6
5
4
3
2
1
0
TIE
RIE
TE
RE
REIE
—
CKE1 CKE0
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
The SCSCR2 register performs enabling or disabling of SCIF transfer operations, serial clock
output, and interrupt requests, and selection of the serial clock source.
SCSCR2 can be read or written to by the CPU at all times.
SCSCR2 is initialized to H'0000 by a power-on reset or manual reset. It is not initialized in
standby mode or in the module standby state.
Bits 15 to 8, and 2—Reserved: These bits are always read as 0, and should only be written with
0.
Bit 7—Transmit Interrupt Enable (TIE): Enables or disables transmit-FIFO-data-empty
interrupt (TXI) request generation when serial transmit data is transferred from SCFTDR2 to
SCTSR2, the number of data bytes in the transmit FIFO register falls to or below the transmit
trigger set number, and the TDFE flag in the serial status register (SCFSR2) is set to 1.
Bit 7: TIE
Description
0
Transmit-FIFO-data-empty interrupt (TXI) request disabled* (Initial value)
1
Transmit-FIFO-data-empty interrupt (TXI) request enabled
Note: * TXI interrupt requests can be cleared by writing transmit data exceeding the transmit trigger
set number to SCFTDR2 after reading 1 from the TDFE flag, then clearing it to 0, or by
clearing the TIE bit to 0.
Bit 6—Receive Interrupt Enable (RIE): Enables or disables generation of a receive-data-full
interrupt (RXI) request when the RDF flag or DR flag in SCFSR2 is set to 1, a receive-error
interrupt (ERI) request when the ER flag in SCFSR2 is set to 1, and a break interrupt (BRI)
request when the BRK flag in SCFSR2 or the ORER flag in SCLSR2 is set to 1.
Rev. 3.0, 04/02, page 641 of 1064