HD6417751 Datasheet, PDF (588/1105 Pages) Renesas Technology Corp – SuperH RISC engine

b. If a DMA transfer request for channel 0 is input during execution of a channel 0 DMA bus
cycle, the DDT will ignore that request. Confirm that channel 0 DMA transfer has finished
(burst mode) or that a DMA bus cycle is not in progress (cycle steal mode).
7. DTR format
a. The DDT module processes DTR.ID, DTR.MD, and DTR.SZ as follows.
When DTR.ID= 00
• MD = 00, SZ ≠ 101, 110: Handshake protocol using the data bus
• MD ≠ 00, SZ = 111: CHCR0.DE = 0 setting (DMA transfer end request)
• MD = 10, SZ = 110: DDT request queue clear
When DTR.ID ≠ 00
• Transfer request to channels 1—3 (items other than ID ignored)
8. Data transfer end request
a. A data transfer end request (DTR.ID = 00, MD ≠ 00, SZ = 111) cannot be accepted during
channel 0 DMA transfer. Therefore, if edge detection and burst mode are set for channel 0,
transfer cannot be ended midway.
b. When a transfer end request (DTR.ID = 00, MD ≠ 00, SZ = 111) is accepted, the values set
in CHCR0.SAR0, DAR0, and DMATCR0 are retained. In this case, execution cannot be
restarted from an external device. To restart execution, set CHCR0.DE = 1 with an MOV
instruction.
9. Request queue clearance
a. When settings of DTR.ID = 00, DTR.MD = 10, and SZ = 110 are accepted by the DDT in
normal data transfer mode, DDT channel 0 requests and channel 1 to 3 request queues are
all cleared. All external requests held on the DMAC side are also cleared.
b. In case 3-c, the DMAC freeze state can be cleared.
c. When settings of DMAOR.DDT = 1, DTR.ID = 00, DTR.MD = 10, and SZ = 110 are
accepted by the DDT in case 11, the DMAC freeze state can be cleared.
10. '%5(4 assertion
a. After '%5(4 is asserted, do not assert '%5(4 again until %$9/ is asserted, as this will
result in a discrepancy between the number of '%5(4 and %$9/ assertions.
b. The %$9/ assertion period due to '%5(4 assertion is one cycle.
If a row address miss occurs in a read or write in the non-precharged bank during
synchronous DRAM access, %$9/ is asserted for a number of cycles in accordance with
the RAS precharge interval set in BSC.MCR.TCP.
c. It takes one cycle for '%5(4 to be accepted by the DMAC after being asserted by an
external device. If a row address miss occurs at this time in a read or write in the non-
precharged bank during synchronous DRAM access, and %$9/ is asserted, the '%5(4
signal asserted by the external device is ignored. Therefore, %$9/ is not asserted again
due to this signal.
Rev. 3.0, 04/02, page 548 of 1064